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Hardware Acceleration of BLOB Detection for Image Processing

  • This paper presents the implementation and evaluation of a computer vision task on a Field Programmable Gate Array (FPGA). As an experimental approach for an application-specific image-processing problem, it provides results about gained performance and precision compared with similar solutions on General Purpose Processor (GPP) architectures. The problem of detecting Binary Large OBjects (BLOBs) in a continuous video stream and computation of their center points has been addressed. Most existing solutions are realized on GPP platforms, where resolution of image material and sequential processing define the performance barrier. FPGA based approaches perform implemented algorithms as fast as hardware circuits and in addition offer parallelization abilities. The evaluation compares precision and performance gain against similar approaches on GPP platforms. The paper discusses different concepts for BLOB detection and shows the implementation of one common method for BLOB detection, including design problems and performance evaluation.

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Metadaten
Document Type:Conference Object
Language:English
Parent Title (English):Third International Conference on Advances in Circuits, Electronics and Micro-Electronics (CENICS). Venice, 18-25 July 2010
First Page:28
Last Page:33
ISBN:978-1-4244-7535-3
DOI:https://doi.org/10.1109/CENICS.2010.12
Publisher:IEEE
Date of first publication:2010/08/26
Tag:Blob Detection; FPGA; Image Processing; Parallelization; SystemVerilog
Departments, institutes and facilities:Fachbereich Informatik
Institute of Visual Computing (IVC)
Dewey Decimal Classification (DDC):000 Informatik, Informationswissenschaft, allgemeine Werke / 000 Informatik, Wissen, Systeme / 004 Datenverarbeitung; Informatik
Entry in this database:2015/04/02