• search hit 4 of 107
Back to Result List

Visualization Support for FPGA Architecture Exploration

  • Nowadays Field Programmable Gate Arrays (FPGA) are used in many fields of research, e.g. to create prototypes of hardware or in applications where hardware functionality has to be changed more frequently. Boolean circuits, which can be implemented by FPGAs are the compiled result of hardware description languages such as Verilog or VHDL. Odin II is a tool, which supports developers in the research of FPGA based applications and FPGA architecture exploration by providing a framework for compilation and verification. In combination with the tools ABC, T-VPACK and VPR, Odin II is part of a CAD flow, which compiles Verilog source code that targets specific hardware resources. This paper describes the development of a graphical user interface as part of Odin II. The goal is to visualize the results of these tools in order to explore the changing structure during the compilation and optimization processes, which can be helpful to research new FPGA architectures and improve the workflow.

Export metadata

Additional Services

Share in Twitter Search Google Scholar Availability
Document Type:Report
Parent Title (English):Technical Report / Faculty of Computer Science, University of New Brunswick
Publisher:University of New Brunswick
Publication year:2011
Departments, institutes and facilities:Fachbereich Informatik
Institute of Visual Computing (IVC)
Dewey Decimal Classification (DDC):0 Informatik, Informationswissenschaft, allgemeine Werke / 00 Informatik, Wissen, Systeme / 004 Datenverarbeitung; Informatik
Entry in this database:2015/04/02