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FPGA-based image combiner for parallel rendering

  • Rendering of virtual scenes is an application that still demands higher computing power for more complex and more realistic scenes. In addition to existing parallel processing inside a graphics processing unit, this paper investigates a further level of parallelization. A combiner based on an FPGA (field programmable gate array) allows to merge the graphics output of several independent computers. The image combiner supports different load distribution techniques, namely sort-first and sort-last rendering. A system prototype based on a commercial evaluation system proved the viability of the approach. A compact and cost-efficient dedicated implementation has been designed and is used as a platform to investigate different approaches for parallel rendering.

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Metadaten
Document Type:Conference Object
Language:English
Parent Title (English):IEEE International Conference on Signal and Image Processing Applications (ICSIPA), 16-18 Nov. 2011, Kuala Lumpur, Malaysia
First Page:427
Last Page:432
ISBN:978-1-4577-0243-3
DOI:https://doi.org/10.1109/ICSIPA.2011.6144067
Publication year:2011
Tag:FPGA based image combiner; commercial evaluation system; cost efficient dedicated implementation; field programmable gate array; graphic processing unit; load distribution techniques; parallel processing; parallel rendering; sort-first rendering; sort-last rendering; virtual scene rendering
Departments, institutes and facilities:Fachbereich Informatik
Fachbereich Elektrotechnik, Maschinenbau, Technikjournalismus
Institute of Visual Computing (IVC)
Dewey Decimal Classification (DDC):6 Technik, Medizin, angewandte Wissenschaften / 60 Technik
0 Informatik, Informationswissenschaft, allgemeine Werke / 00 Informatik, Wissen, Systeme / 004 Datenverarbeitung; Informatik
Entry in this database:2015/04/02