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Nowadays Field Programmable Gate Arrays (FPGA) are used in many fields of research, e.g. to create prototypes of hardware or in applications where hardware functionality has to be changed more frequently. Boolean circuits, which can be implemented by FPGAs are the compiled result of hardware description languages such as Verilog or VHDL. Odin II is a tool, which supports developers in the research of FPGA based applications and FPGA architecture exploration by providing a framework for compilation and verification. In combination with the tools ABC, T-VPACK and VPR, Odin II is part of a CAD flow, which compiles Verilog source code that targets specific hardware resources. This paper describes the development of a graphical user interface as part of Odin II. The goal is to visualize the results of these tools in order to explore the changing structure during the compilation and optimization processes, which can be helpful to research new FPGA architectures and improve the workflow.
Field Programmable Gate Arrays (FPGA) are used in many fields of research, e.g. to create prototypes of hardware or in applications where hardware functionality has to be changed more frequently. Boolean circuits, which can be implemented by FPGAs are the compiled result of hardware description languages such as Verilog or VHDL. Odin II is a tool, which supports developers in the research of FPGA based applications and FPGA architecture exploration by providing a framework for compilation and verification. In combination with the tools ABC, T-VPACK and VPR, Odin II is part of a CAD flow, which compiles Verilog source code that targets specific hardware resources. This paper describes the development of a graphical user interface as part of Odin II. The goal is to visualize the results of these tools in order to explore the changing structure during the compilation and optimization processes, which can be helpful to research new FPGA architectures and improve the work flow.
Field-programmable gate arrays (FPGAs) are integrated circuits that can be designed or configured after manufacturing. They are used in many disciplines to create prototypes of hardware or in applications where hardware functionality needs to be changed more frequently. Design of new FPGA architectures requires tools that allow developers to create new structures and test those structures in order to compare the results to already established solutions. Boolean circuits, implemented on the FPGAs are compiled using hardware description languages such as Verilog or VHDL. The VTR (Verilog to Routing) CAD (Computer Aided Design) tool, compiles Verilog source code that targets specific hardware resources as FPGAs and ASICs (Application Specific Integrated Circuits). The VTR CAD tool consists of three tools: Odin II, for elaboration from Verilog to a netlist, ABC, for logic synthesis, and VPR, for physical synthesis and analysis. Odin II currently supports only a sub-set of constructs in Verilog language. This paper describes improved and expanded language support for Verilog elaboration introduced in Odin II, in order to provide developers with a tool set to assist in modern FPGA research. With this enhanced language support, a subsequent evaluation of the performance characteristics of VTR flow with a set of benchmarks that are supported by VTR is performed.
Developing applications for Field Programmable Gate Array (FPGA) devices utilizes Computer Aided Design (CAD) flows. The transition from a high level Verilog hardware description to the optimized structure of programmed soft logic blocks and routing structure includes stages such as Verilog synthesis, hardware mapping, logical synthesis, packing, placement and routing. The VTR CAD flow is a collaborative project consisting of Odin II (University of New Brunswick), ABC (University of California, Berkeley) and VPR (University of Toronto), which offers an FPGA CAD flow for research and experimentation purposes. This paper describes developments in the visualization and simulation modules of Odin II, the first stage of the CAD flow. The contributions include new netlist visualization possibilities as well as an extended netlist simulator capable of simulating circuits with multiple clocks and providing extended generic structure simulation abilities. This results in the possibility to explore and simulate a larger set of new FPGA architectures and evaluate them using the VTR flow.
Nowadays perception is still an up-to-date scienti fic issue on a mobile robot system. This thesis introduces an approach on how to recognize objects, namely numbers, using a digital camera on a Volksbot robot. The robot used in this thesis has been specifi cally designed for the SICK robot day. The development of the vision algorithm was done in two stages: the region of interest detection and the actual number recognition. Diff erent algorithms had been tested and evaluated and the Canny edge detector with contour finding has been proven to be the best choice for the region of interest detection and the Tesseract OCR engine was the best decision for number recognition. To integrate the vision component on an existing robot system, ROS was used. This thesis also discusses the integration of the EPOS motor controller into ROS.
