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Die Erfindung betrifft eine elektrische Insektenabwehrvorrichtung (1) zur Abwehr kriechender Insekten (2) umfassend eine Spannungserzeugungseinrichtung (4a, 4b) zur Erzeugung einer Abwehrspannung sowie umfassend zumindest zwei nebeneinander angeordnete und beabstandet zueinander verlaufende blanke elektrische Leiter (5a, 5b, 5c, 5d), die derart mit der Spannungserzeugungseinrichtung (4a, 4b) verbunden sind, dass die Abwehrspannung zwischen ihnen liegt. Die elektrischen Leiter sind als flache Leiterbahnen (5a, 5b, 5c, 5d) auf oder in der Oberfläche eines gemeinsamen Trägers (12, 13, 50, 60) ausgebildet, so dass ein Insekt (2) bei einem Berühren der Leiterbahnen (5a, 5b, 5c, 5d) einen elektrischen Schlag erhält.
High peak to average power ratio (PAPR) of a transmitted signal is one of the major drawbacks of the complex wavelet packet modulation (CWPM) as usual in any multicarrier communication system. Utilizing the advantage of concentrating the energy to certain subspaces of the discrete wavelet transform, many PAPR reduction techniques are proposed to solve this problem like threshold and clipping methods. In this paper a novel hybrid PAPR reduction method for CWPM called Threshold-Clipping (TC) method has been proposed. The simulation results in Rayleigh multipath fading channel show that the proposed scheme has achieved 4.5 dB and 3 dB reduction in PAPR over the traditional threshold and clipping methods respectively with less than 0.5 dB degradation in bit error probability.
In this paper, the performance evaluation of Frequency Modulated Chaotic On-Off Keying (FM-COOK) in AWGN, Rayleigh and Rician fading channels is given. The simulation results show that an improvement in BER can be gained by incorporating the FM modulation with COOK for SNR values less than 10dB in AWGN case and less than 6dB for Rayleigh and Rician fading channels.
The paper presents the design of a baseband pi/4-DQPSK complex wavelet packet modulation CWPM transceiver and the results of its FPGA implementation. The design uses 8-point Discrete Wavelet Packet Transform (DWPT) and its inverse as core processing modules. All modules have been designed using VHDL programming language together with the Altera software tools Quartus II 9.1 and ModelSim 6.5b. The transceiver was implemented on a Cyclone III board.
The main requirements of efficient steganographic systems are transparency, robustness and security. In this work, the proposed system is designed to achieve these requirements, as follows: to increase the transparency and robustness, the proposed system uses the transform domain technique, in this case the wavelet domain technique to embed the color secret image into the color cover image. To achieve high security, chaotic systems are used to accomplish the following two purposes: firstly to scramble the secret color image before hiding it into the color cover image, secondly to randomly select the embedding positions in the cover image. Three chaotic systems with many combinations are used for the scrambling and the embedding process. Experimental results including Mean Square Error (MSE), Peak Signal to Noise Ratio (PSNR), Correlation, Signal to Noise Ratio (SNR) and embedding capacity demonstrate that the proposed system has good performance as compared with other existing methods without attack and under different types of attacks such as filtering and noise attacks. Simulation results show that the combination of chaotic systems providing the best performance include the use of Logistic and Hénon maps for the embedding process and Arnold's cat map for the encryption process. The MSE, PSNR, correlation, SNR and embedding capacity obtained in this case reach up to 0.0010, 78.1dB, 0.9999, 67.2dB and 0.39% respectively when the secret image is Airplane with 32×32 pixels and the cover image is Girl with 512×512 pixels. For the extracted secret image, the chaotic system set that provides the best performance includes the use of Arnold's cat map for the encryption process. The MSE, PSNR, correlation and SNR obtained in this case reach up to 0.0846, 58.9dB, 1 and 56.1dB respectively. As compared with other methods, the proposed method achieves gains without any attack of 8.2dB for the stego image and 32.4dB for the extracted secret image in PSNR when the secret image is Airplane with 256×256 pixels and the cover image is Girl with 512×512 pixels.
This paper presents an efficient design and implementation of a complex wavelet packet modulation (CWPM) multicarrier communication transceiver using an FPGA platform. A fast algorithm already proposed for high data rate WPM systems has been applied to CWPM systems for speed enhancement. The theoretical performance of the computation algorithm is analyzed. The design uses 16-point Fast Wavelet Packet Transform/Inverse Wavelet Packet Transform (FWPT/IFWPT) of the Haar family as the core processing module. All the proposed fast CWPM (FCWPM) system modules are designed and implemented using VHDL programming language. Software tools used in this work include Altera Quartus II 9.1 and ModelSim Altera 6.5b. A Cyclone III board is used for the implementation. The hardware simulation results show that the use of fast Haar wavelet packet transform algorithms to implement complex wavelet packet modulation systems significantly increases its speed as compared with direct implementations.
Cost efficient energy monitoring in existing large buildings demands for autonomous indoor sensors with low power consumption, high performance in multipath fading channels and economic implementation. Good performance in multipath fading channels can be achieved with noncoherent chaotic modulation schemes such as chaos on-off keying (COOK) or differential chaos shift keying (DCSK). While COOK stands out in the area of power consumption, DCSK excels when it comes to its performance in noisy and multipath fading channels. This paper evaluates a combination of both schemes for autonomous indoor sensors. The simulation results show 50% less power consumption than DCSK and more than 3dB SNR gain in Rayleigh fading channels at BER=10-3 as compared to COOK, making it a promising candidate for low power transmission in autonomous wireless indoor sensors. We further present an enhanced version of this scheme showing another 1 dB SNR improvement, but at 25% less power consumption than DCSK.
The requirements of an efficient communication scheme for wireless sensing applications have been investigated. The noncoherent direct chaotic communication scheme called chaos on-off keying (COOK) has presented itself as a promising candidate. This paper proposes a modified version of the COOK scheme to improve its performance in noisy and fading environments. The proposed scheme is designed to increase the signal space of the decision variable by using the concept of differential correlation keeping implementation requirements simple. The results show that the proposed modified version of the COOK scheme achieves less bit-error probability in noisy and fading channels at moderate signal-to-noise ratio values and almost constant detection threshold as compared with the original version.
Energy consumption awareness is an important first step to reduce carbon emissions. While real time fuel consumption indicators in motor vehicles are widespread, the instant energy consumption of buildings is typically unknown. This paper presents a multisensor system for energy consumption awareness in large, existing buildings that offers real time consumption values of all energy types at low-costs and with little installation efforts. The system aims at educating, motivating and supporting the inhabitants to save energy and reduce their carbon footprint. Sensor data fusion is used to enhance measurement quality while keeping costs low.
Design and Analysis of an OFDM-Based Orthogonal Chaotic Vector Shift Keying Communication System
(2018)
We propose a new non-coherent multicarrier spread-spectrum system that combines orthogonal chaotic vector shift keying (OCVSK) and orthogonal frequency-division multiplexing (OFDM). The system enhances OCVSK by sending multiple groups of information sequences with the same orthogonal chaotic vector reference sequences over the selected subcarriers. Each group carries M information bits and is separated from other groups by orthogonal chaotic reference signals. We derive the information rate enhancement (IRE) and the energy saving enhancement (ESE) factors as well as the bit error rate theory of OFDM-OCVSK under additive white Gaussian noise and multipath Rayleigh fading channels and compare the results with conventional OCVSK systems. For large group numbers, the results show that the IRE and ESE factors approachM×100% andM/(M+1)×100%, respectively, and thus outperform OCVSK systems. The complexity analysis of the proposed scheme as compared with OFDM-DCSK shows a significant reduction in the number of complex multiplications required.
En el siguiente trabajo se presentan las diferentes alternativas tecnológicas que brindarán soporte para las comunicaciones en el Proyecto Campo Conectado, priorizando el bajo consumo y mantenimiento. Esta plataforma de transmisión proveerá la conectividad necesaria para la recolección y envío de los datos requeridos por los productores agropecuarios, con el fin de mejorar la gestión de los procesos productivos y comerciales. Se comenta además los orígenes del proyecto y los actores involucrados en el mismo, destacándose el trabajo interinstitucional e interdisciplinar que se lleva a cabo.
This paper presents the design procedure and implementation results of an amplitude modulation (AM) double sideband – Large carrier (DSB-LC) receiver using an Altera FPGA EP3C120 development board. The design is first implemented in MATLAB/Simulink(TM) using also embedded MATLAB(TM) blocks. It is then automatically converted to VHDL level with the Simulink HDL coder. The VHDL code is then synthesized and fitted with QuartusII ®; software and downloaded to the Altera CycloneIII EP3C120 FPGA development board. The results show that this approach makes it is easy for students to understand and develop the reception of AM signals using programmable logic tools. It also presents an efficient design flow for realizing design modules using MATLAB.
