Fachbereich Elektrotechnik, Maschinenbau, Technikjournalismus
This paper presents the design procedure and implementation results of an amplitude modulation (AM) double sideband – Large carrier (DSB-LC) receiver using an Altera FPGA EP3C120 development board. The design is first implemented in MATLAB/Simulink(TM) using also embedded MATLAB(TM) blocks. It is then automatically converted to VHDL level with the Simulink HDL coder. The VHDL code is then synthesized and fitted with QuartusII ®; software and downloaded to the Altera CycloneIII EP3C120 FPGA development board. The results show that this approach makes it is easy for students to understand and develop the reception of AM signals using programmable logic tools. It also presents an efficient design flow for realizing design modules using MATLAB.
