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Visualization support for FPGA architecture exploration

  • Field Programmable Gate Arrays (FPGA) are used in many fields of research, e.g. to create prototypes of hardware or in applications where hardware functionality has to be changed more frequently. Boolean circuits, which can be implemented by FPGAs are the compiled result of hardware description languages such as Verilog or VHDL. Odin II is a tool, which supports developers in the research of FPGA based applications and FPGA architecture exploration by providing a framework for compilation and verification. In combination with the tools ABC, T-VPACK and VPR, Odin II is part of a CAD flow, which compiles Verilog source code that targets specific hardware resources. This paper describes the development of a graphical user interface as part of Odin II. The goal is to visualize the results of these tools in order to explore the changing structure during the compilation and optimization processes, which can be helpful to research new FPGA architectures and improve the work flow.

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Metadaten
Document Type:Conference Object
Language:English
Parent Title (English):23rd IEEE International Symposium on Rapid System Prototyping (RSP), 11-12 Oct. 2012, Tampere
First Page:128
Last Page:134
ISBN:978-1-4673-2786-2
DOI:https://doi.org/10.1109/RSP.2012.6380701
Publisher:IEEE
Date of first publication:2012/12/13
Tag:Boolean circuits; CAD flow; Design automation; FPGA architecture exploration; Graphical user interfaces; Hardware; Hardware design languages; Integrated circuit interconnections; Odin II; VHDL; Verilog source code; Visualization; field programmable gate arrays; graphical user interface; hardware description languages; hardware functionality; hardware resources; visualization support
Departments, institutes and facilities:Fachbereich Informatik
Dewey Decimal Classification (DDC):000 Informatik, Informationswissenschaft, allgemeine Werke / 000 Informatik, Wissen, Systeme / 004 Datenverarbeitung; Informatik
Entry in this database:2015/04/02