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Visual exploration of changing FPGA architectures in the VTR project

  • Developing applications for Field Programmable Gate Array (FPGA) devices utilizes Computer Aided Design (CAD) flows. The transition from a high level Verilog hardware description to the optimized structure of programmed soft logic blocks and routing structure includes stages such as Verilog synthesis, hardware mapping, logical synthesis, packing, placement and routing. The VTR CAD flow is a collaborative project consisting of Odin II (University of New Brunswick), ABC (University of California, Berkeley) and VPR (University of Toronto), which offers an FPGA CAD flow for research and experimentation purposes. This paper describes developments in the visualization and simulation modules of Odin II, the first stage of the CAD flow. The contributions include new netlist visualization possibilities as well as an extended netlist simulator capable of simulating circuits with multiple clocks and providing extended generic structure simulation abilities. This results in the possibility to explore and simulate a larger set of new FPGA architectures and evaluate them using the VTR flow.

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Metadaten
Document Type:Conference Object
Language:English
Parent Title (English):2013 International Symposium on Rapid System Prototyping (RSP), Montreal, QC, Canada, 3-4 Oct. 2013
First Page:16
Last Page:22
ISBN:978-1-4799-2410-3
DOI:https://doi.org/10.1109/RSP.2013.6683953
Publisher:IEEE
Date of first publication:2013/12/16
Departments, institutes and facilities:Fachbereich Informatik
Institute of Visual Computing (IVC)
Dewey Decimal Classification (DDC):000 Informatik, Informationswissenschaft, allgemeine Werke / 000 Informatik, Wissen, Systeme / 004 Datenverarbeitung; Informatik
Entry in this database:2016/07/22