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In this paper, a set of micro-benchmarks is proposed to determine basic performance parameters of single-node mainstream hardware architectures for High Performance Computing. Performance parameters of recent processors, including those of accelerators, are determined. The investigated systems are Intel server processor architectures and the two accelerator lines Intel Xeon Phi and Nvidia graphic processors. Additionally, the performance impact of thread mapping on multiprocessors and Intel Xeon Phi is shown. The results show similarities for some parameters between all architectures, but significant differences for others.
IT-accessiblity is often treated as an orphan in companies. Even though the proportion of disabled people is substantial and people become older and more susceptible to disabilities. Besides cost factors, companies often do not have a plan how to implement and control IT-accessibility successfully. However, most companies are familiar with IT-maturity frameworks to evaluate and improve their own IT-infrastructure. It would facilitate dealing with IT-accessibility, if IT-maturity frameworks consider IT-accessibility and provide recommendations and solutions for a successful implementation. Therefore, this article conducts a review of an acknowledged IT-maturity framework with regard to its capability to enable implementation of IT-accessibility in an organization. The first part of this article will illustrate the motivation and background for the authors concern with such a topic. Afterwards the authors will introduce the reader to the reviewed IT-maturity framework and provide basic knowledge on IT-accessibility. The main part of the article will deal with the review of the applied IT-maturity framework and outline examples of critical capabilities for successfully implementing IT-accessibility in an organization. The final section will derive implications and close with planned future research activities in this field.
The Render Cache [1,2] allows the interactive display of very large scenes, rendered with complex global illumination models, by decoupling camera movement from the costly scene sampling process. In this paper, the distributed execution of the individual components of the Render Cache on a PC cluster is shown to be a viable alternative to the shared memory implementation.As the processing power of an entire node can be dedicated to a single component, more advanced algorithms may be examined. Modular functional units also lead to increased flexibility, useful in research as well as industrial applications.We introduce a new strategy for view-driven scene sampling, as well as support for multiple camera viewpoints generated from the same cache. Stereo display and a CAVE multi-camera setup have been implemented.The use of the highly portable and inter-operable CORBA networking API simplifies the integration of most existing pixel-based renderers. So far, three renderers (C++ and Java) have been adapted to function within our framework.