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Classification and comparative analysis of fast median filter structures

  • The classification of median filter hardware structure was proposed. Main differences, advantages and disadvantages of each class were described. Scalable and synthesizable Verilog-descriptions were designed for two fast hardware structures. HDL-descriptions were synthesized on Altera and Xilinx FPGA platforms, comparative analysis on the basis of resource utilization and clock rate was done.

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Metadaten
Document Type:Conference Object
Language:English
Author:Ivan Osadchiy, Dmitry Kaleev, Alexey Pereverzev, Roustiam Chakirov
Parent Title (English):Picking, Cunningham et al. (Eds.): 2015 Internet Technologies and Applications (ITA). Proceedings of the Sixth International Conference (ITA 15). Wrexham, United Kingdom, 8-11 Sept. 2015
First Page:29
Last Page:32
ISBN:978-1-4799-8036-9
DOI:https://doi.org/10.1109/ITechA.2015.7317364
Publisher:IEEE
Date of first publication:2015/11/05
Departments, institutes and facilities:Fachbereich Elektrotechnik, Maschinenbau, Technikjournalismus
Institut für Technik, Ressourcenschonung und Energieeffizienz (TREE)
Entry in this database:2016/03/03